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基于PCIe的高速数据采集卡的FPGA设计与实现

发布时间:2019-01-08 08:10  文章来源:笔耕文化传播
【摘要】:随着数据采集系统的广泛应用,国内与国外的技术水平仍存在一定的差距,研发一款具有自主知识产权的高速数据采集系统显得越来越迫切,本论文课题背景是研究一款6GSPS采样率、1GHz带宽的高速数据采集卡,本论文主要研究的内容是基于PCIe总线技术的高速AD采集卡的数据存储与控制。 在硬件设计中,为了提高系统的采样速率,采用两片ADC芯片时间并行交替采样的方法。在可编程逻辑设计中,FPGA作为设计的主控模块,采用模块化的设计思路使用VHDL语言实现对FPGA的控制,逻辑设计部分主要包括:基于SPI的串行通信设计实现时钟芯片以及ADC芯片内部寄存器的配置;使用FPGA内部资源MIG控制核实现DDR2SDRAM高速数据的存取和读写控制;数据采集卡与上位机的通信采用PCIe总线接口,,使用可编程逻辑的器件Virtex5芯片生成PCIe端点IP核的方法实现,从而大大缩短了开发周期,简化了设计流程;设计基于DMA方式的PCIe总线传输,数据传输过程中,不需要占用CPU资源却可以实现更高的实际传输速率。 本设计和PCIe总线驱动相结合,成功实现了上位机通过PCIe总线对数据采集卡各芯片的配置,也实现了数据采集卡向上位机传输AD采样数据并存储的功能,结合仿真软件Modelsim和检测FPGA内部信号的ChipScope软件对系统功能进行调试和验证,从而证实了该方案的可行性。
[Abstract]:With the wide application of data acquisition system, there is still a certain gap between domestic and foreign technology level, so it is more and more urgent to develop a high-speed data acquisition system with independent intellectual property rights. The background of this thesis is to study a high speed data acquisition card with 6GSPS sampling rate and 1GHz bandwidth. The main content of this paper is the data storage and control of high speed AD acquisition card based on PCIe bus technology. In the hardware design, in order to improve the sampling rate of the system, two ADC chips were sampled in parallel. In the programmable logic design, FPGA is used as the main control module of the design, and the modular design idea is adopted to realize the control of FPGA by using VHDL language. The logic design mainly includes: the serial communication design based on SPI realizes the clock chip and the ADC chip internal register configuration; Using FPGA internal resource MIG control core to realize DDR2SDRAM high-speed data access and read and write control; The communication between the data acquisition card and the host computer adopts the PCIe bus interface, and the PCIe endpoint IP core is generated by the programmable logic device Virtex5 chip, which greatly shortens the development cycle and simplifies the design process. The PCIe bus transmission based on DMA mode is designed. In the process of data transmission, higher actual transmission rate can be achieved without taking up CPU resources. The design is combined with the PCIe bus driver, which realizes the configuration of each chip of the data acquisition card by the PCIe bus, and also realizes the function of transmitting the AD sampling data and storing the data from the data acquisition card to the host computer. The system function is debugged and verified by combining the simulation software Modelsim and the ChipScope software which detects the internal signal of FPGA, which proves the feasibility of the scheme.
【学位授予单位】:电子科技大学
【学位级别】:硕士
【学位授予年份】:2013
【分类号】:TP274.2

【参考文献】

相关期刊论文 前3条

1 王伟;傅其祥;;基于PCIe总线的超高速信号采集卡的设计[J];电子设计工程;2010年05期

2 吕喜在;张宝文;赵德鑫;苏绍t

本文编号:2404335


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